The present invention relates to a semiconductor protective device, and to a method of manufacturing a semiconductor protective device.
More particularly, it relates to an on-chip static electricity protective element in a semiconductor device comprising a fine-featured complimentary MOS semiconductor integrated circuit having a minimum interconnect width of 0.5 micron or less.
In the past, a semiconductor on-chip static electricity protective technology of this type has been known to persons skilled in the art, from the following literature, for example.
More specifically, as shown in FIG. 6, the U.S. Pat. No. 5,502,317 has a disclosure of an N well 142 formed on the surface of a P-type semiconductor substrate 126, a P-type diffusion layer 146 and N-type diffusion layer 144 connected to an external terminal formed therein, and N-type diffusion layer 114 formed on a semiconductor substrate 126 part of which is included in the N well 142, an N-type diffusion layer 112 connected to a ground terminal 118 and an N-type diffusion layer 122 formed on the semiconductor substrate 126, via an element separation region 124.
In this known semiconductor protective device, when an excessive positive static electricity voltage is applied to the external terminal, the PN junction formed by the N-type diffusion layer 114 and the P-type semiconductor substrate 126 exhibits an avalanche breakdown, thereby raising the potential on the substrate.
Because of this action, the NPN transistor formed by the N-type diffusion layer 114, the P-type semiconductor substrate 126, and the N-type diffusion layer 112 conducts.
Because of this, the potential in the region of the P-type diffusion layer 146 of the N well 142 decreases, so that the PNP transistor formed by the P-type diffusion layer 146, the N well 142, and the P-type semiconductor substrate 126 conducts.
As a result, the NPN transistor and PNP transistor operate in a complimentary manner so as to enhance the collector current, the result being entry into the low-resistance condition of so-called thyristor operation, thereby enabling protection of the internal circuit by causing a current to flow.
In the U.S. Pat. No. 5,872,379, which is a similar example of prior art, as shown in FIG. 7, the basic configuration is the same as shown in FIG. 6, the major difference between FIG. 6 and FIG. 7 configurations being that, in place of the element separation region 124 shown in FIG. 6, in FIG. 7 a P-type diffusion layer 38 having a P-LDD structure is formed, the reverse withstand voltage of the PN junction at the boundary 40 between the P-type diffusion layer 38 and the N-type diffusion layer 20 being decreased, so that the trigger voltage for thyristor operation is lowered, thereby improving the protective capacity.
This type of semiconductor protective element of the past is effective with respect to an external pulse having a slow rise time. However, it is poor in protective capacity with respect to a pulse having a fast rise time.
In particular, there is a known charged device model (CDM) mode static pulse in which the rise time is extremely fast, this being 500 ps or shorter, and having a large discharge current of 10 A or more, thereby causing failures of the gate oxide film or the like in a fine-featured MOS LSI element. The protective element of the past is particularly troubled with a low capacity to provide protection for such fast mode static pulses as these.
By various simulations, the inventors, as a result of an investigation of the cause of the low protective capacity of this type of protective element with respect to a CDM mode pulse, were able to discover the cause thereof.
Specifically, there are two causes, which differ depending upon whether the overvoltage is positive or negative.
For example, in the first case, in which a positive overvoltage is applied to a semiconductor protective element of this type from the prior art, the element operates as a thyristor, but the starting speed is slow, so that a voltage greater than the breakdown voltage is applied to the internal circuit, thereby causing a low breakdown withstand voltage with respect to a fast pulse.
Additionally, in accordance with the simulations performed by the inventors, it was discovered that the starting speed is dependent upon the distance Dac between the anode and the cathode electrodes of the thyristor element.
Specifically, FIG. 10 shows the results of a simulation for the case in which a thyristor element of the past is used as a protective element, with a CDM mode static electricity pulse of 1000 V applied, in which the relationship between the voltage VoxMAX applied to the internal circuitry to be protected and the distance Dac between the anode and cathode of the thyristor element is shown.
As is clear from FIG. 10, to reduce the maximum voltage VoxMAX applied to the internal circuit, it is necessary to reduce the distance Dac between the anode electrode and the cathode electrode of the thyristor element.
However, it was difficult to reduce this distance with the structure of the past. That is, in FIG. 6, which shows the configuration of prior art as disclosed in the U.S. Pat. No. 5,502,317, the reference numeral 146 denotes the anode electrode and 112 denotes the cathode electrode, there being an N-type diffusion layer 114 and element separation film 124 therebetween, which restricts the reduction of the anode-to-cathode distance Dac.
In FIG. 7, which shows the configuration of the specification of the U.S. Pat. No. 5,872,379 which discloses prior art, the reference numeral 34 denotes the anode electrode and 18 denotes the cathode electrode, between which are interposed an N-type diffusion layer 20 and a P-type diffusion layer 38, which make reduction of Dac difficult.
The second case is that in which a negative CDM mode pulse is applied to a protective element of the past. The reason for a reduction in protective capacity in this case is that the element operates as a diode, wherein parasitic resistance of the element causes a rise in the voltage of the circuit to be protected.
That is, in the case of a CDM mode static discharge, because of the large discharge current, with even a small parasitic resistance, there is a rise in the voltage generated at the element terminals, thereby causing breakdown of the internal circuit.
The inventors discovered by their simulations that the parasitic resistance is substantially proportional to the distance between the diode cathode and anode. It is therefore desirable to reduce the distance between the cathode and the anode of the diode, although this was difficult to achieve in the structure of the past.
Specifically, in the structure disclosed in U.S. Pat. No. 5,872,379, for diode operation, the N-type diffusion layer 20 acts as the cathode electrode and the P-type diffusion layer 14 acts as the anode electrode, with an N-type electrode 18 and a P-type electrode 38 interposed therebetween, so that there is a limitation on the reduction of the distance therebetween that can be achieved.
Additionally, in Japanese Patent No. 2669245, there is disclosure of a configuration which uses a junction-type field effect transistor as a protective element.
However, there is no language therein with regard to technology for using a protective circuit having a thyristor structure with respect to CDM mode static discharge in a fine-featured semiconductor device.
Additionally, in the Japanese Unexamined Patent Publication (KOKAI) No. 59-181044, there is disclosure of a configuration which uses a protective circuit having two diode and resistance stages as a gate protective circuit for an MOS FET. However, there is no language therein with regard to technology for using a protective circuit with a thyristor structure with respect to a CDM mode static discharge in a fine-featured semiconductor device.
Additionally, in the Japanese Unexamined Patent Application S62-165966, there is indicated a configuration in which a Zener diode is used as a protective circuit for a semiconductor element. However, there is no language therein with regard to technology for using a protective circuit having a thyristor structure with respect to a CDM mode static discharge in a fine-featured semiconductor device, similar to the case of the previously noted disclosure.
In the Japanese Unexamined Patent Publication (KOKAI) No. 9-223748, there is disclosure of a configuration in which, as a protective circuit, a diode and the parallel connection of an MOS FET and protective transistor are connected to the input terminals. However, similar to the case of the foregoing disclosure, there is no language therein with regard to technology for using a protective circuit having a thyristor structure with respect to a CDM mode static discharge in a fine-featured semiconductor device.
In the Japanese Unexamined Patent Publication (KOKAI) No. 9-191082, there is disclosure of a technology for using a thyristor structure as a protective circuit for a CMOS circuit. However, the basic configuration is a vertical-type MOS, and because an oxide film is formed as a separating layer between the thyristor structure, the distance between electrodes is lengthened, thereby making it impossible to accommodate high-speed pulses.
In this disclosure, there is no language with regard to technology for driving a diode as a trigger for the thyristor.
Accordingly, it is an object of the present invention, in order to improve on the drawbacks of the above-noted prior art, to provide a protective element structure which, without the addition of a special process step when manufacturing, for example, in a CMOS LSI of the past, enables on-substrate fabrication, and further provides high protection capacity with respect to a fast pulse such as a CDM mode static pulse. It is a further object of the present invention to provide a method for manufacturing a semiconductor protective device.
In order to achieve the above-noted object, the present invention has the following basic technical constitution.
Specifically, a first aspect of the present invention is a semiconductor protective device having a first well of a first conductive type, a second well of a second conductive type, being directly connected to said first well, a third well of a first conductive type being directly connected to one side of said second well which being opposite to the side thereof to which said first well being connected, each three wells being formed on a substrate, a first diffusion layer of a first conducive type formed within said second well of the second conductive type, a second diffusion layer of a second conducive type formed within said first well of said first conductive type and provided in proximal opposition to said first diffusion layer, a third diffusion layer of a second conductive type provided at a position over a boundary portion of said second well of a second conductive type and said third well of a first conductive type so as to bridge therebetween, said position being different from a position over a boundary portion of said second well of a second conductive type and said first well of a first conductive type where said first diffusion layer and said second diffusion layer being arranged in proximal opposition, and a fourth diffusion layer of a first conductive type provided within said third well of said first conductive type and which formed in proximate opposition to said third diffusion layer of said second conductive type, wherein said first and said third diffusion layers are connected to a first terminal, while said second and said fourth diffusion layers being connected to a second terminal.
A second aspect of the present invention is a method for manufacturing a semiconductor protective device, this method having a step of disposing a first mask material on at least part of a semiconductor substrate and implanting a second conductivity ion therein to form a second well of a second conductivity type, a step of forming a second mask material minimally in a region in which said second well region is formed and implanting a first conductivity ion in a region that is directly in contact with said second well region but outside said second well region, so as to form a first well of first conductivity type and a third well of a first conductivity type, a step of forming a third mask material having a first aperture formed at a position opposite a region that minimally bridges said third well region and said second well region and a second aperture formed at a position in said first well region and nearly opposite to said second well of said second conductivity type region, and implanting a second conductivity ion, so as to form a third and a second diffusion layers of said second conductivity, respectively, a step of forming a fourth mask material having a third aperture formed in said second well region, minimally at a position corresponding to a region in proximal opposition to said second diffusion layer formed in said first well region and a fourth aperture formed at a position in said third well region and corresponding to a region in proximal opposition to said third diffusion region in said second well region, and implanting a first conductivity ion so as to form a first diffusion layer and a fourth diffusion layer of said first conductivity type, respectively.
By adopting the above-noted constitution, a semiconductor protective device and method for manufacturing a semiconductor protective device according to the present invention provide a thyristor element having the first diffusion layer as an anode and the second diffusion layer as a cathode, which operates in this manner when a positive overvoltage pulse is applied.
Under the above condition, it is possible to reduce the distance between the anode and the cathode within the limits of manufacturing technology for LSI devices. For example, in the case of a CMOS LSI device having a 0.25 xcexcm design rule, this distance can be established as 1 xcexcm or smaller.
Therefore, even if a fast positive static pulse, such as a CDM mode pulse is applied, the response speed of the protective element is fast, thereby enabling limitation of the voltage rise applied to the circuit under protection.
In the case of a negative overvoltage, the operation is as a diode having the third diffusion layer as a cathode and the fourth diffusion layer as an anode. In this case, because it is also possible to reduce the distance between the cathode and the anode within the limits of manufacturing technology, it is possible to form a diode with extremely low internal resistance. For this reason, even in the case of an excessive discharge current value, it is possible to limit the voltage rise in the internal circuit.